architecture - VHDL Finite State Machine -

how can implement vhdl code designs finite state machine without letting compiler knows it's finite state machine. in code given you'll see how implemented fsm in class, showed state diagram in rtl viewer, how can not let compiler know it's fsm , not draw state diagram. moreover, professor said design faster if compiler doesn't recognise fsm.

library ieee;   use ieee.std_logic_1164.all;   entity fsm     port ( clk, reset, x1 : in std_logic;                       outp : out std_logic);   end entity;   architecture beh1 of fsm     type state_type (s1,s2,s3,s4);     signal state, next_state: state_type ;   begin    process1: process (clk,reset)     begin       if (reset ='1')         state <=s1;       elsif (clk='1' , clk'event)         state <= next_state;       end if;     end process process1;     process2 : process (state, x1)     begin       case state             when s1 => if x1='1'                            next_state <= s2;                         else                           next_state <= s3;                         end if;             when s2 => next_state <= s4;             when s3 => next_state <= s4;             when s4 => next_state <= s1;       end case;   end process process2;   process3 : process (state)     begin         case state             when s1 => outp <= '1';             when s2 => outp <= '1';             when s3 => outp <= '0';             when s4 => outp <= '0';         end case;   end process process3;   end beh1;  

the synthesized design not neccessarily faster or smaller if state machine extraction disabled because synthesis compiler can choose several encodings when synthesizing state machine. can turn off state machine extraction via menu "assignments" -> "settings" -> "analysis & synthesis settings" -> "more settings" -> "extract vhdl state machines".

let's start default setting extraction on. if use cyclone iv fpga example, synthesis compiler choose one-hot encoding state-machine. see in compilation report under "analysis & synthesis" -> "state machines". 4 combinational functions (luts) , 3 logic registers required. first estimate of speed of design can deduced synthesized netlist accessible via menu "tools" -> "netlist viewers" -> "technology map viewer (post-mapping)":

(clickable)

as see, there maximum of:

• 1 levels of logic between 2 registers
• 1 levels of logic between input , register
• 1 levels of logic between output , register

so pretty fast , final timing merely depend on routing delay.

if disable fsm extraction, 2 luts , 2 registers required because state encoded binary. netlist like:

(clickable)

there small improvement: output can directly driven register state[1]. design have smaller clock-to-output time.

here improvement possible after state machine extraction turned off. but, not case because depends on actual encoding of type state_type. if leave fsm extraction disabled , change declaration of state_type to:

  type state_type (s3,s1,s2,s4);   

then synthesis result worse again: 3 luts , 2 registers required, , 1 level of logic between register , output.