enhancing a VHDL code for a mips processor main decoder block -

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i new vhdl programming , here want enhance following code in point :

entity maindec   port(op: in std_logic_vector(5 downto 0); memtoreg, memwrite: out std_logic; branch, alusrc: out std_logic; regdst, regwrite: out std_logic; --jump: out std_logic; aluop: out std_logic_vector(1 downto 0));  -- declarations  end maindec ;  -- hds interface_end architecture untitled of maindec signal controls: std_logic_vector(8 downto 0); signal jump_2 : std_logic; begin process(op)  begin case op when "000000" => controls <= "110000010"; -- rtype when "100011" => controls <= "101001000"; -- lw when "101011" => controls <= "001010000"; -- sw when "000100" => controls <= "000100001"; -- beq when "001000" => controls <= "101000000"; -- addi when "000010" => controls <= "000000100"; -- j when others => controls <= "---------"; -- illegal op end case; end process; regwrite<=controls(8); regdst<=controls(7); alusrc<=controls(6); branch<=controls(5); memwrite<=controls(4); memtoreg<=controls(3); jump_2<=controls(2); aluop<=controls(1 downto 0);  end untitled;

this main decoder block in mips processor , required build mips processor. in block required controls signal 9 bits. @ same time jump output must not exists in block , facing problem in destroying third bit of controls signal , have removed jump out signal entity , have created random signal , have passed third bit of controller signal. problem here , think not efficient way , because when done port map of whole processor module , got many warnings because of problem. 1 can suggest way solve problem ?


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